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HIGH DYNAMIC RANGE IP

Implementation of proprietary High Dynamic Range video display algorithm on multiple semiconductor platforms

 The Need

  • Implementing a real time hardware IP for a Tier 1 multimedia company with a proprietary software algorithm
  • Multiple implementations targeting different chipsets in the Digital TV and Set Top Box markets
  • Be at the forefront in an ever-competitive Consumer Electronics market

 Our Contribution

  • Create an implementation with the smallest possible FPGA, meeting the high-frequency targets needed for UHD processing, FPGA-based implementation already being in market
  • Create ASIC IPs for the Digital TV and Set Top Box SoCs
  • Work directly with multiple DTV SoC semiconductor companies, ODMs and TV manufacturers for IP Specification creation, implementation and final qualification
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