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RTL Design Engineer (2-5 years of experience)

Responsible for RTL design, SoC integration and work hands-on in the development cycle

Must have

  • Hands-on experience and expert-level knowledge in RTL design and coding
  • Hands-on experience and expert-level knowledge in SoC integration of ARM core based designs
  • Experience in working with AMBA Bus- AXI, AHB, APB
  • In-depth understanding of Verilog/VHDL and ARM SoC architecture
  • Hands-on experience and expert-level knowledge in ASIC Synthesis
  • Hands-on experience and expert-level knowledge in Static Timing Analysis
  • Experience in equivalency checking Preferred
  • Experience in Ethernet, PCIe
  • Experience in networking domain
  • Experience in PERL, TCL. Python

Tools  Cadence / Synopsys tool sets

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