- Admin
- February 24, 2025

Case Study
Cortex M3 Based Security Authentication SoC

Client
Cortex M3 based Security authentication chip with real time boot decryption engine, battery backed up tamper protection unit and USB based finger print authentication interface for a Tier 1 Semiconductor Company
Challenges
• SoC integration and system IP design
• IO Mux Design
• Bridge IP design
• Low power implementation
• LINT, CDC, Conformal checks
• Synthesis and Post Layout STA
• Working closely with PD and DFT team till tape-out
Solution
• Low Power SoC
• Multiple power mode support
• Multiple Voltage domain
• Memory retention
• Clock fault monitor and switching schemes
Tools/Technologies
SV-UVM, NCSIM, Conformal LP