PHYSICAL DESIGN (PD)
Beyond Place N Route.
![](https://ignitarium.com/wp-content/uploads/2024/02/png-devider-234x34x0x0x234x34x1628668901.png)
Ownership mode Physical Design from RTL to Power, Performance and Area optimized GDS. Expertise in FinFET-based nanometer-scale technology nodes and industry leading tool flows to bring precision and predictability to your complex physical implementation requirements.
Do it right with Ignitarium.
Our Offerings
![png-devider-210x32x0x0x210x30x1628668901 png-devider-210x32x0x0x210x30x1628668901](https://ignitarium.com/wp-content/uploads/elementor/thumbs/png-devider-210x32x0x0x210x30x1628668901-qlhhqj7fan5yex6vi642c2qpfqvve9m8ery6ipmjfa.png)
- Advanced-Node Implementations
- Flip-chip and Wire-bond designs
- Pad ring design and Bump planning
- Low power, Multi-voltage, Multi-island implementations
- Full-chip and Block-level Floor planning & Power planning
- Physical synthesis
- PPA aware Placement
- Advanced Clock-Tree implementations
- Power Integrity Closure
- Signal Integrity Closure
- Functional, Timing & DRV ECOs
- Full-chip and Block-level Timing Closure
- Physical Verification
- Chip Finishing
- Tape-out & Foundry Interface
PD Stages
STAGE 01
In-bound Collateral QA
- Netlist integrity checks
- SDC integrity checks
- UPF integrity checks
- Library QA
- View QA (eg. LEF vs GDS)
- Tech file checks
- Rule file checks
![](https://ignitarium.com/wp-content/uploads/2024/02/QA-v0.2-688x674x0x0x688x674x1688096652-300x294.png)
![](https://ignitarium.com/wp-content/uploads/2024/02/IMAGE1-IO-Planning-1-752x738x0x0x752x738x1687840463-300x294.png)
STAGE 02
IO Planning
- Define Bond Pad / Bump positions
- Create Pad ring / positions
- ESD Checks
- SSO Checks
STAGE 03
Floor Planning
- Define Core and die dimensions
- Pin Placement
- Macro placement
- Halo assignment
- Cell pre-placement
![](https://ignitarium.com/wp-content/uploads/2024/02/IMAGE2-Floor-Planning-1-698x684x0x0x698x684x1687850334-300x294.png)
![](https://ignitarium.com/wp-content/uploads/2024/02/IMAGE3-Power-Planning-1-946x926x0x0x946x926x1687840603.png)
STAGE 04
Power Planning
- Connect Global nets
- Create Power Rings
- Create Power Stripes
- Create Special Routes
- Logic Equivalence Check
- IR, EM Analysis
- Physical Verification
STAGE 05
Placement
- Coarse Placement
- Legalization
- High Fanout Net Synthesis
- Timing optimization
- Power optimization
- Scan-Chain Reordering
- Logic Equivalence Check
- Incremental Placement
![](https://ignitarium.com/wp-content/uploads/2024/02/IMAGE4-1-688x674x0x0x688x674x1687840624-300x294.png)
![](https://ignitarium.com/wp-content/uploads/2024/02/IMAGE5-Clock-Tree-Synthesis-1-750x736x0x0x750x736x1687840642.png)
STAGE 06
Clock Tree Synthesis
- Timing Optimization
- Delay Balancing
- Latency Improvement
- DRV optimization
- Logic Equivalence Check
STAGE 07
Routing
- Global Routing
- Track Assignment
- Detail Routing
- Search & Repair
- Incremental Routing
- Timing Analysis
![](https://ignitarium.com/wp-content/uploads/2024/02/Routing-1-692x678x0x0x692x678x1687840663-300x294.png)
![](https://ignitarium.com/wp-content/uploads/2024/02/IMAGE7-Fill-Finish-1-752x738x0x0x752x738x1687840696-300x294.png)
STAGE 08
Fill & Finish
- Add Fillers
- Add PFC
- Add Metal Fill
- Add logo & fiducials
STAGE 09
Extraction
- Multi-interconnect corner RC correlation
- 2.5D or 3D extraction
- Detail RoSPEF generation uting
- SPEF generation
![](https://ignitarium.com/wp-content/uploads/2024/02/IMAGE8-Extraction-1-728x714x0x0x728x714x1687840724-300x294.png)
![](https://ignitarium.com/wp-content/uploads/2024/02/IMAGE9-Static-Timing-Analysis-1-902x884x0x0x902x884x1687840752.png)
STAGE 10
Static Timing Analysis
- Set-up Check
- Hold Check
- DRV Check
- Pulse Width Check
- Duty Cycle Check
- Crosstalk Noise Check
- Crosstalk Delay Check
STAGE 11
IR & Power Analysis
- Static IR Drop
- Dynamic IR Drop
- Signal and Power EM
- Power Switch Coverage
- Secondary PG Coverage
- Static Power Analysis
- Dynamic Power Analysis
- Leakage Recovery
![](https://ignitarium.com/wp-content/uploads/2024/02/IR-DROP-1-678x666x0x0x678x666x1687840836-300x294.png)
![](https://ignitarium.com/wp-content/uploads/2024/02/Physical-Verification-762x748x0x0x762x748x1687840858-300x294.png)
STAGE 12
Physical Verification
- ERC
- DRC
- LVS
- Density Checks
- XOR Checks
- DFM
STAGE 13
Tape-Out
- Base Layer Tapeout
- Metal Layer Tapeout
- Foundry interface
- e-Job view
![](https://ignitarium.com/wp-content/uploads/2024/02/SILICON-WAFER-1-684x670x0x0x684x670x1687850391-300x294.png)