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DESIGN FOR TEST (DFT)

Crafting designs for zero-defect manufacturing.

Offering top-quality and highly-efficient DFT process and methodology with in-depth experience in all EDA tools to enable a design with the highest coverage and lowest test times. 

Do it right with Ignitarium.

Our Offerings

DFT architecture definition

RTL modification for DFT-friendly design

Low power and topographical synthesis

Hierarchical DFT implementation and full-chip porting

DFT SDC generation for STA

DFT (JTAG, SCAN, MBIST) insertion and verification

ATPG pattern generation and Timing simulation

Test coverage analysis and improvement

Post-silicon pattern delivery and pattern debug

DFT DRC checks and fixes

DFT Stages

1 - Architecture and Planning

IO scan channel, pin usage and block chains allocation planning

BSCAN-JTAG, MBIST-JTAG, IP_JTAG sharing

SCAN flow – Hierarchical / compression, OCC placement

3 rd party IP integration

Block level and Top-level signal planning

Low power planning

2 - DFT Implementation

SCAN,OCC,COMP insertion

MBIST, Repair insertion

JTAG & BSCAN insertion

Logic Equivalence check

Block to Top integration

DFT DRC cleanup and suggestion for DRC fix.

DFT Lint cleanup

3 - PATTERN Generation & Validation

JTAG/BSCAN/SCAN/MBIST pattern generation and validation at block level and chip-top level.

Gate level simulation of Patterns - both zero delay and with timing

Testcase analysis and Improvement

Pattern delivery

Pattern debug

4 - DFT Constraints and STA Signoff

Scan shift mode

Scan capture mode

Scan TF mode

Mbist mode

Jtag mode

Bscan mode

Step 1

Architecture and Planning

IO scan channel, pin usage and block chains allocation planning

BSCAN-JTAG, MBIST-JTAG, IP_JTAG sharing

SCAN flow – Hierarchical / compression, OCC placement

3rd party IP integration

Block level and Top-level signal planning

Low power planning

Step 2

DFT Implementation

SCAN, OCC, COMP insertion

MBIST, Repair insertion

JTAG & BSCAN insertion

Logic Equivalence check

Block to Top integration

DFT DRC cleanup and suggestion for DRC fix

DFT Lint cleanup

Step 3

PATTERN Generation & Validation

JTAG/BSCAN/SCAN/MBIST pattern generation and validation at block level and chip-top level

Gate level simulation of Patterns - both zero delay and with timing

Testcase analysis and Improvement

Pattern delivery

Pattern debug

Step 4

DFT Constraints and STA Signoff

Scan shift mode

Scan capture mode

Scan TF mode

Mbist mode

Jtag mode

Bscan mode