LLM Assisted Code Coverage Closure | Technical Paper

Large Language Models (LLMs) are in the limelight ever since their potential has been realized in the field of natural language processing.

The capabilities of LLMs including summarization, code generation and code analysis can be effectively used in the VLSI design flow. Verification consumes a large part of a typical System On Chip (SoC) or Intellectual Property (IP) design cycle. Methods to accelerate this phase would be greatly beneficial to chip design project timelines.

In this paper, we describe an LLM-enabled methodology to speed up the verification phase by automatically generating test coverage waivers from a design specification document.