- Team Marketing
- October 8, 2024
Reducing Power Hot Spots through RTL optimization techniques | Technical Paper
With the tremendous increase in the intelligence added to various consumer and professional devices, the applications are turning more data-centric and computation intensive.
From the IC design perspective, this enhances the already existing challenge of power vs area trade-off. Power Analysis is not a new terminology in the semiconductor design cycle. But there is a difference in opinion regarding the most efficient phase of the design cycle for power analysis.
An architecture phase will be too early, and physical design phase will be too late for the power estimation. Of late, there is a tendency to analyze power hot spots during the RTL phase of the project. RTL based power analysis is faster and easier to perform and has a shorter iteration time than the analysis at later stages. This article addresses some of the power optimization techniques applied at the RTL level.
