A cost-effective debug solution using OpenOCD for hardware platforms

A cost-effective debug solution using OpenOCD for hardware platforms

In today’s world, hardware platforms are growing in complexity and reducing the time to market for these platforms is key to capturing the market segment. Gone are the days when the hardware was considered as a critical piece; customers now expect the board to be delivered as a package containing world-class hardware infrastructure with reliable & robust software to run complex applications. This brings the need to equip the engineers with the right set of tools to get them started to meet these challenges and work effectively.

Software development starts early, right at the pre-silicon stage, using reference boards or FPGA platforms. Having a sophisticated debug infrastructure is an important part of development of these software systems. The infrastructure helps in two aspects 1) in recreating some of the corner case scenarios while testing the software which otherwise might not have been possible and 2) any issues that are seen in the software can be recreated and isolated providing engineers the capability to quickly debug the software. 

For this debugging phase, a well-known interface that many engineers rely on, is the JTAG. Manufacturers provide JTAG to empower engineers with complete access to test and program integrated circuits.


Different types of JTAG debuggers

There are several powerful tools provided by third party vendors capitalizing the JTAG interface for debugging. However, these devices do not come cheap and investing in such a tool for multiple hardware platforms is sure to shoot up your overall costs exponentially. So, is there a possibility to get similar flexibility at a fraction of the cost? This blog intends to address just this, by introducing the JTAG interface as well as providing a low-cost solution to engineers by combining OpenOCD software for debugging via JTAG.

What is JTAG ?

JTAG is an IEEE standard (1149.1) developed in the 1980s to solve electronic boards manufacturing issues. It is primarily used for verifying designs and testing printed circuit boards after manufacture. In short, it is a hardware interface to communicate directly with the chips on a board. 

In the past, tests on PCBs (Printed Circuit Boards) were done through a system called bed-of-nails. PCB was designed with several test points to be connected to this test board to perform checks. 


Testing via a bed of nails

A few novel uses of a JTAG are

  • Connect to a hardware device to read / write from its memory
  • Dump RAM and gain access to sensitive data such as passwords and cryptographic keys
  • Inject instructions directly into the pipeline of the target chip 
  • Activate peripherals and change their behavior, such as setting or resetting an I/O pin
  • Access Flash Memory to update and or modify the firmware of a device

JTAG Architecture

Basic architecture of the JTAG circuitry consists of a set of Data Registers (DR), set of Instruction Registers (IR), a finite state machine (FSM) to arbitrate data and four pin serial interface. Discussing and detailing the FSM is beyond the scope of this blog.

The JTAG specification IEEE 1149.1 specifies not only the signals but how the “State Machine” embedded in the TAP (Test Access Port) Controller of a device must behave. So, the JTAG interface requires a minimum of 4 pins to communicate with the chip. These signals, and silicon logic that connects and controls them, are collectively referred to as the Test Access Port, or TAP controller.

  • TCK (Test Clock) – The actual clock speed is not specified in the JTAG standard. The TAP controller accepts its speed from the outside device controlling JTAG.
  • TMS(Test Mode Select) – Used as an input into the TAP controller
  • TDI (Test Data In) – A pin to feed data into the chip and what the chip does with them is irrelevant to JTAG.
  • TDO (Test Data Out) -The pin for data coming out of the chip. 
  • [Optional]TRST(Test Reset)- This optional signal is used to reset JTAG to a known good state.

JTAG state machine

Note that 

  • data is read into and out of the TDI and TDO pins while the state machine is in the Shift-IR or Shift-DR states.
  • The IR (Instruction Register) and DR (Data Register) are like function calls. 
  • The value in IR is the “function” and the value in DR is the “argument”. 
  • The JTAG specification doesn’t define what the “functions” should be, that’s up to the manufacturer. 

Interesting thing to note is that keeping TMS high for more than 5 clock cycles brings the state machine from any state back to the test logic reset state. Thus, a separate TRST pin is optional and not necessary.

TAP(Test Access Port) 

ANSI/IEEE Standard 1149.1-1990, (Standard Access Port and Boundary-Scan Architecture) defines test logic that can be included on an integrated circuit to provide standardized approaches to testing the component itself or the interconnections between components on a printed circuit board. 

The test logic allows test instructions and test data to be fed to a component, and upon execution of an instruction, allows the results to be read out and observed. All instructions, test data, and results are communicated in serial format. The test logic defined by the standard consists of a chain of boundary-scan cells and test support logic, which are accessed through the TAP inputs.

Schematic Diagram of JTAG enabled Device

TAP (Test Access port) can be considered as the controller which initiates different internal tests, provides access to internal registers based upon the instruction registers assigned to it.. 

Every TAP is expected to have an IDCode Register holding a unique Identity Code to differentiate and recognize it. The primary step in JTAG debugging is to identify the TAP connected to the interface and use the appropriate IR/DR (Instruction/Data Registers) set to access the internal chip resources. One of the most powerful tools you can pair with JTAG, to unlock the true potential of this interface via automation is OpenOCD. Automation coupled with remote access to various stations remotely is a key requirement here and OpenOCD provides just that — an intuitive interface that can be tailored to your needs and different SoC architectures.

OpenOCD (Open On-Chip Debugger)

OpenOCD is the only Open Source debugging software tool/repository (knowledge base) for a variety of chips and interfaces. This can (when paired with a JTAG interface device) manipulate the JTAG’s TAP controller on a target device to send bits to it (via the state machine above), which the chip will interpret as valid commands.

Support for OpenOCD requires certain information regarding the device to properly sequence JTAG signals for communication and thus we need to write  a configuration file capturing the device architecture. Config files for many of the most common chip types are included within the OpenOCD and new ones need to be written for custom designer chips.

OpenOCD lets you perform all the basic operations you would expect like pause, step through an operation, inspect memory, write bytes directly into memory, set watch-points, add breakpoints, and more complex operations like inject code into the process or process memory. This technique is called “Hardware Based Software Debugging” as we are manipulating the hardware to perform traditional software debugging tasks. For a new core which is not supported, the framework has to be modified to support these operations. 

As mentioned earlier, the software is open source and available for anyone to use as required. Ignitarium has been providing custom  JTAG + OpenOCD solutions for chip design / verification teams (of various chip manufacturers) to run their validation tests on their chips having non-standard complex JTAG daisy chains. 

One of the main challenges with ASIC / SoC having  multicore architecture is the debugging of its various blocks. For a  bringup of  new silicon, as most of you are aware, the first trusted tool is the JTAG, which in its traditional CLI form can be time consuming and cumbersome to work with. OpenOCD coupled with JTAG can considerably reduce the time for the entire activity. However, this support also requires adding the respective debug structures to be separately integrated into the OpenOCD software layer so as to enable normal and complex debug setup for these chips in an automated fashion. 

Ignitarium has the expertise of adding this support for  cores which are not supported as part of the open-source software. In one such case, a customer had multiple instances of IP cores integrated with non-standard bus architecture. We provided a custom solution by modifying the software layer, such that it can communicate with these cores using the bus standard implemented on the chip and enabling support to debug these multiple core instances. 

References

  1. JTAG Primer
  2. Coresight debug Architecture
  3. Technical guide to JTAG
  4. OpenOCD Source Repo
  5. JTAG Fundamentals

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    Founder and Managing director of Ignitarium, Sanjay has been responsible for defining Ignitarium’s core values, which encompass the organisation’s approach towards clients, partners, and all internal stakeholders, and in establishing an innovation and value-driven organisational culture.

     

    Prior to founding Ignitarium in 2012, Sanjay spent the initial 22 years of his career with the VLSI and Systems Business unit at Wipro Technologies. In his formative years, Sanjay worked in diverse engineering roles in Electronic hardware design, ASIC design, and custom library development. Sanjay later handled a flagship – multi-million dollar, 600-engineer strong – Semiconductor & Embedded account owning complete Delivery and Business responsibility.

     

    Sanjay graduated in Electronics and Communication Engineering from College of Engineering, Trivandrum, and has a Postgraduate degree in Microelectronics from BITS Pilani.

     

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      RAMESH EMANI

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      Ramesh was the Founder and CEO of Insta Health Solutions, a software products company focused on providing complete hospital and clinic management solutions for hospitals and clinics in India, the Middle East, Southeast Asia, and Africa. He raised Series A funds from Inventus Capital and then subsequently sold the company to Practo Technologies, India. Post-sale, he held the role of SVP and Head of the Insta BU for 4 years. He has now retired from full-time employment and is working as a consultant and board member.

       

      Prior to Insta, Ramesh had a 25-year-long career at Wipro Technologies where he was the President of the $1B Telecom and Product Engineering Solutions business heading a team of 19,000 people with a truly global operations footprint. Among his other key roles at Wipro, he was a member of Wipro's Corporate Executive Council and was Chief Technology Officer.

       

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      Ramesh holds an M-Tech in Computer Science from IIT-Kanpur.

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      Ashwin strongly believes in the customer-first approach and works to add value and enhance the experiences of our customers.

       

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      Prior to joining Ignitarium in 2017, Pradeep was Senior Solutions Architect at Open-Silicon, an ASIC design house. At Open-Silicon, where he spent a good five years, Pradeep was responsible for Front-end, FPGA, and embedded SW business development, marketing & technical sales and also drove the IoT R&D roadmap. Pradeep started his professional career in 2000 at Sasken, where he worked for 11 years, primarily as an embedded multimedia expert, and then went on to lead the Multimedia software IP team.

      Pradeep is a graduate in Electronics & Communication from RVCE, Bangalore.

       

      SUJEET SREENIVASAN Vice President – Embedded

      SUJEET SREENIVASAN

      Vice President – Automotive Technology

       

      Sujeet is responsible for driving innovation in Automotive software, identifying Automotive technology trends and advancements, evaluating their potential impact, and development of solutions to meet the needs of our Automotive customers.

      At Ignitarium, he was previously responsible for the growth and P&L of the Embedded Business unit focusing on Multimedia, Automotive, and Platform software.

      Prior to joining Ignitarium in 2016, Sujeet has had a career spanning more than 16 years at Wipro. During this stint, he has played diverse roles from Solution Architect to Presales Lead covering various domains. His technical expertise lies in the areas of Telecom, Embedded Systems, Wireless, Networking, SoC modeling, and Automotive. He has been honored as a Distinguished Member of the Technical Staff at Wipro and has multiple patents granted in the areas of Networking and IoT Security.

      Sujeet holds a degree in Computer Science from Government Engineering College, Thrissur.

       

      RAJIN RAVIMONY Distinguished Engineer

      RAJIN RAVIMONY

      Distinguished Engineer

       

      At Ignitarium, Rajin plays the role of Distinguished Engineer for complex SoCs and systems. He's an expert in ARM-based designs having architected more than a dozen SoCs and played hands-on design roles in several tens more. His core areas of specialization include security and functional safety architecture (IEC61508 and ISO26262) of automotive systems, RTL implementation of math intensive signal processing blocks as well as design of video processing and related multimedia blocks.

       

      Prior to Ignitarium, Rajin worked at Wipro Technologies for 14 years where he held roles of architect and consultant for several VLSI designs in the automotive and consumer domains.

       

      Rajin holds an MS in Micro-electronics from BITS Pilani.

       

      SIBY ABRAHAM Executive Vice President, Strategy

      SIBY ABRAHAM

      Executive Vice President, Strategy

       

      As EVP, of Strategy at Ignitarium, Siby anchors multiple functions spanning investor community relations, business growth, technology initiatives as well and operational excellence.

       

      Siby has over 31 years of experience in the semiconductor industry. In his last role at Wipro Technologies, he headed the Semiconductor Industry Practice Group where he was responsible for business growth and engineering delivery for all of Wipro’s semiconductor customers. Prior to that, he held a vast array of crucial roles at Wipro including Chief Technologist & Vice President, CTO Office, Global Delivery Head for Product Engineering Services, Business Head of Semiconductor & Consumer Electronics, and Head of Unified Competency Framework. He was instrumental in growing Wipro’s semiconductor business to over $100 million within 5 years and turning around its Consumer Electronics business in less than 2 years. In addition, he was the Engineering Manager for Enthink Inc., a semiconductor IP-focused subsidiary of Wipro. Prior to that, Siby was the Technical Lead for several of the most prestigious system engineering projects executed by Wipro R&D.

       

      Siby has held a host of deeply impactful positions, which included representing Wipro in various World Economic Forum working groups on Industrial IOT and as a member of IEEE’s IOT Steering Committee.

       

      He completed his MTech. in Electrical Engineering (Information and Control) from IIT, Kanpur and his BTech. from NIT, Calicut

       

      SUJEETH JOSEPH Chief Product Officer

      SUJEETH JOSEPH

      Chief Technology Officer

       

      As CTO, Sujeeth is responsible for defining the technology roadmap, driving IP & solution development, and transitioning these technology components into practically deployable product engineering use cases.

       

      With a career spanning over 30+ years, Sujeeth Joseph is a semiconductor industry veteran in the SoC, System and Product architecture space. At SanDisk India, he was Director of Architecture for the USD $2B Removable Products Group. Simultaneously, he also headed the SanDisk India Patenting function, the Retail Competitive Analysis Group and drove academic research programs with premier Indian academic Institutes. Prior to SanDisk, he was Chief Architect of the Semiconductor & Systems BU (SnS) of Wipro Technologies. Over a 19-year career at Wipro, he has played hands-on and leadership roles across all phases of the ASIC and System design flow.

       

      He graduated in Electronics Engineering from Bombay University in 1991.

       

      SUJITH MATHEW IYPE Co-founder & CTO

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      Co-founder & COO

       

      As Ignitarium's Co-founder and COO, Sujith is responsible for driving the operational efficiency and streamlining process across the organization. He is also responsible for the growth and P&L of the Semiconductor Business Unit.

       

      Apart from establishing a compelling story in VLSI, Sujith was responsible for Ignitarium's foray into nascent technology areas like AI, ML, Computer Vision, and IoT, nurturing them in our R&D Lab - "The Crucible".

       

      Prior to founding Ignitarium, Sujith played the role of a VLSI architect at Wipro Technologies for 13 years. In true hands-on mode, he has built ASICs and FPGAs for the Multimedia, Telecommunication, and Healthcare domains and has provided technical leadership for many flagship projects executed by Wipro.

       

      Sujith graduated from NIT - Calicut in the year 2000 in Electronics and Communications Engineering and thereafter he has successfully completed a one-year executive program in Business Management from IIM Calcutta.

       

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      RAMESH SHANMUGHAM

      Co-founder & CRO

      As Co-founder and Chief Revenue Officer of Ignitarium, Ramesh has been responsible for global business and marketing as well as building trusted customer relationships upholding the company's core values.

      Ramesh has over 25 years of experience in the Semiconductor Industry covering all aspects of IC design. Prior to Ignitarium, Ramesh was a key member of the senior management team of the semiconductor division at Wipro Technologies. Ramesh has played key roles in Semiconductor Delivery and Pre-sales at a global level.

      Ramesh graduated in Electronics Engineering from Model Engineering College, Cochin, and has a Postgraduate degree in Microelectronics from BITS Pilani.