PowerBots in PowerArtist featured image

PowerBots in PowerArtist for Early-Power Analysis and Reduction: An Introduction

Early power analysis in System-on-chip (SoC) design is a hot topic today. The power budget of electronic devices is decreasing every day even though area and complexity are increasing. The situation is the same for wired and wireless devices. A wireless device cannot afford to have higher power simply because that will increase the battery consumption, whereas for a wired device, high power means an increase in cooling costs. In a design flow, the common practice is to wait until RTL code is complete, then synthesize and run power analysis on the netlist. But it would be difficult to re-visit and re-factor RTL at this stage as that would mean repeating simulation, linting, synthesis, etc. repeatedly which will increase costs substantially. An improved design flow would be the one that accounts for power analysis and reduction at an early stage so that power budgeting is complete as early as possible. There are a few great tools such as ‘Joules RTL power solution’ by Cadence, PowerArtist by Ansys, etc. that does Power Analysis and Power Reduction early in the design cycle. In this blog, we discuss a feature called ‘PowerBots’ by PowerArtist that could be used for early RTL power reduction. 

PowerBots by PowerArtist: 

PowerBots are power reduction modules by PowerArtist. These PowerBots scan the design, looking for a specific design feature and then perform analysis and checks to make recommendations on power saving numbers or power wastage numbers to help make the decision to save power. If PowerBots can determine an example change for the design, then it could also provide a code snippet. The figure below shows how PowerBots fit into the PowerArtist. 

PowerBots in PowerArtist

There are basically two types of PowerBots used – ‘Power Reduction PowerBots’ and ‘Power Linter PowerBots’. ‘Power Reduction PowerBots’ look at the implementation and will try to analyse power saving, power penalty and area impact for a different implementation technique. While ‘Power Linter PowerBots’ help to identify the areas of the design where power is wasted. Power Linter PowerBots do not recommend a means of recovering the wasted power, as the method of recovering depends heavily on the design and test pattern. Listed below are different PowerBots supported: 

  1. Power Reduction PowerBots 
    a. Low-Activity Non-Enabled Register (LNR) 
    b. Datapath Operator Isolation (DOI) 
    c. Local Explicit Clock Enable (LEC) 
    d. Split Memory Words (SMW) 
    e. Gate Memory Clock (GMC) 
    f. Power Reduction in State Machines (PRISM) 
    g. Observability Don’t Care (ODC) 

  1. Power Linter PowerBots 
    a. Clock Enable Condition Linter (CEC) 
    b. Memory Power Linter (MEM) 
    c. Register Power Linter (REG) 
    d. MUX Power Linter (MUX) 

Power Reduction PowerBots: 

Low-Activity Non-Enabled Register (LNR) PowerBot: 

This PowerBot identifies and reports all Registers in the design that don’t change frequently and does not have an enable. The PowerBot will also estimate the savings gained if a clock enable is generated based on the change in register input. An example design is shown as below: 

In the above circuit, power is wasted as most of the clock toggles are un-used and unnecessary. It would be great, if the clock is gated so that the clock gets enabled only when ‘D’ input changes. But note that there is also an impact on the area when extra logic is added to save power. 

Datapath Operator Isolation (DOI) PowerBot: 

The LNR PowerBot as explained in the previous section suggests adding enable for Registers especially when it’s a low-activity Register. But consider if a clock enable is present and there are datapath operators such as a multiply or add in front of the enabled register. DOI PowerBot is used here to estimate the power savings gained from latching the datapath inputs when the output is not read. 

For example, the above figure shows datapath operators going to a register that has an explicit clock enable. When the enable is off, the datapath output is ignored by the register though the datapath is consuming power to compute a result. DOI PowerBot will analyze the power saved if the input to the datapath is kept quiet by isolating using the same enable by adding logic like latch as in figure below. 

NOTE: As in most cases, the power saving methodology suggested by the PowerBot could add extra area and a latch could cause negative impact to the timing especially if the datapath is in a critical path. 

Local Explicit Clock Enable (LEC) PowerBot: 

LEC PowerBot is used to estimate power savings if a register that uses ‘a mux in a feedback loop’ as enable is replaced by a gated clock. 

The figure above shows a simple register with a mux-based enable. If D and Q of the register are multi-bit bus and the enable is low for a significant percentage of the circuit operation, then a lot of power is wasted on the clock power. A good synthesis tool with the right constraints could automatically add clock-gate cells for the above circuit during synthesis cycle. But a power analysis report early in the development cycle will give a lot of power to the designer to take the right decisions either to manually insert own clock gate or add the right constraints for synthesis tool to clock gate only those registers that are chosen. 

Split Memory Words (SMW) PowerBot: 

SMW PowerBot is designed to reduce dynamic memory power by splitting a memory into smaller symmetrical and asymmetrical parts. Consider the diagram below that shows a memory with many words split into two smaller memories, each with half the number of words. 

Assume that power of one full-size memory is Fd (Dynamic) and Fs (Static) so that total power (Pf) of the full-size memory (Eg: RAM0) is: 

Pf (RAM0) = Fd + Fs 

SMW PowerBot looks for a memory in the library that is half-size and let’s name it RAM00 and RAM01 with power as Hd (Dynamic) and Hs (Static).  Now if only one (eg: RAM00) of the half-size memory is active, the total power of two Half-Sized memory is: 

Ph (RAM00 + RAM01) = Hd (RAM00) + Hs (RAM00) + Hs (RAM01) 

Power Artist will also consider power consumed by additional circuitry as (Pc) so that the total Power (Pt) will be: 

Pt = Ph + Pc 

SMW accepts memory substitution only if Pt < Pf.   User can set constraints so that SMW will consider splitting memory into more than 2 memories.   

For Eg. If the option is ‘3’ and memory size is 2048×32,  

then SMW will look at options of different smaller memory options such as 3 memories of 1024×32 + 512×32 + 512×32. 

For most architectures, the power of a read or write to the half-sized memory is far less than the power of a read or write to the full-size memories.  SMW PowerBot partitions a memory based on following: 

  • Activity on the MSB and LSB of the address bus 
  • State of the chip enable – it must be active 
  • Whether there is activity on any other bits of the memory 

It selects either LSB or MSB of the address bus – whichever has lower activity. 

NOTE: SMW will also report area overhead for the memory substitutions.  Area and routing congestion are key trade-offs that should be used by a designer to decide the change. 

Gate Memory Clock (GMC) PowerBot: 

GMC PowerBot identifies redundant memory accesses. GMC also identifies redundant write cycles for memories with byte write enables. GMC can determine a way to disable the clock in a redundant read/write access mode. GMC determines memory access as redundant if: 

  • Read/Write data at the memory output does not change or 
  • Read/Write data is not observed in the downstream cone of logic 

GMC can also attempt a different method to identify a memory model that lacks internal clock gating and then turns off the clock when the memory select signal is not asserted. 

GMC during this analysis performs three critical calculations: 

  1. Estimates power saved by implementing potential reduction 

  1. Estimates penalty power to implement additional circuitry for potential reduction 

  1. Estimates Area penalty 

Power Reduction in State Machines (PRISM) PowerBot: 

PRISM PowerBot looks at opportunities where registers that are downstream of enabled registers can also be enabled using a cycle delayed version of those existing enables. PRISM looks for chains of registers where a register early in the chain is enabled while registers later in the chain are not enabled.   The PowerBot will then try to determine if the upstream gated register enable signal can be used to gate it; if so, it will estimate power savings and penalties to determine effectiveness of gating. 

Observability Don’t Care (ODC) PowerBot: 

ODC PowerBot generates enable signals by examining topology of circuit and determine conditions where the outputs of registers are not observable by downstream registers. These conditions are then used as clock enable signals on the upstream register. Depending on the design, this may save a significant amount of dynamic power at the cost of increased area and slight timing impact. 

ODC does the following: 

  • Locates register banks that are not clock-gated, which are the candidate registers 
  • Locates all downstream cone of logic 
  • Locates all 2-1 muxes, unencoded muxes and tri-states in the paths that connect to all downstream registers. These instances form critical steering logic that determines if the register output is observed downstream  
  • PowerBot then examines select lines of all steering logic to determine conditions under which register output is not observable downstream 
  • If such conditions exist, then that becomes a potential candidate for the enable

Power Linter PowerBots: 

Memory Power Linter (MEM) PowerBot: 

MEM PowerBot will monitor the data inputs of all memories in the design to see if the data input ports were wasted because the memory was not selected for a write access. As in the figure below, power is wasted when DATA is toggled more than once but WE is disabled. This behavior could be desirable or undesirable and there are several different ways to implement a more efficient circuit. The PowerBot is essentially an analysis tool that points out the areas of concern. The analysis is very much design and simulation dependent. 

MUX Power Linter (MUX) PowerBot: 

MUX PowerBot will monitor the data inputs of all multiplexers in the design to see if the data input ports were wasted because the data input was not selected. As in the figure below, power is wasted when DATA ‘A’ is toggled more than once while SEL is still ‘0’. This behavior could be desirable or undesirable and there are several different ways to implement a more efficient circuit. The PowerBot is essentially an analysis tool that points out the areas of concern. The analysis is very much design and simulation dependent. 

Register Power Linter (REG) PowerBot: 

REG PowerBot will monitor the data inputs of all registers in the design to see if the data input ports were toggled more than once before the clock of the register completes one cycle. As in the figure below power is wasted when DATA ‘D’ is toggled more than once before CLK completes one cycle. This behavior could be desirable or undesirable and there are several different ways to implement a more efficient circuit. The PowerBot is essentially an analysis tool that points out the areas of concern. The analysis is very much design and simulation dependent. 

Clock Enable Condition Linter (CEC) PowerBot: 

CEC PowerBot will monitor clock gating situations where the data input to the register is driven by a feedback mux. The goal is to determine situations where the mux select line, which acts as the clock gate enable signal, is not optimally designed. As in the figure below, power is wasted when ‘ENABLE’ is high but data ‘D’ doesn’t toggle for some time. This behavior could be desirable or undesirable and there are several different ways to implement a more efficient circuit. The PowerBot is essentially an analysis tool that points out the areas of concern. The analysis is very much design and simulation dependent. 


Power tools are considered as power reporting tools that are used at a later stage of the design cycle.  But features such as PowerBots make it well qualified to be used for early-stage analysis like the way we use Linting and CDC tools, especially if it is a power-critical device. PowerBots can be used at different stages of the design cycle with RTL, mixed RTL, gate, etc. and can be configured as per the design requirements.  

2 thoughts on “PowerBots in PowerArtist for Early-Power Analysis and Reduction: An Introduction”

Leave a Comment

Scroll to Top

Human Pose Detection & Classification

Some Buildings in a city


  • Suitable for real time detection on edge devices
  • Detects human pose / key points and recognizes movement / behavior
  • Light weight deep learning models with good accuracy and performance

Target Markets:

  • Patient Monitoring in Hospitals
  • Surveillance
  • Sports/Exercise Pose Estimation
  • Retail Analytics

OCR / Pattern Recognition

Some Buildings in a city

Use cases :

  • Analog dial reading
  • Digital meter reading
  • Label recognition
  • Document OCR

Highlights :

  • Configurable for text or pattern recognition
  • Simultaneous Analog and Digital Dial reading
  • Lightweight implementation

Behavior Monitoring

Some Buildings in a city

Use cases :

  • Fall Detection
  • Social Distancing

Highlights :

  • Can define region of interest to monitor
  • Multi-subject monitoring
  • Multi-camera monitoring
  • Alarm triggers

Attire & PPE Detection

Some Buildings in a city

Use cases :

  • PPE Checks
  • Disallowed attire checks

Use cases :

  • Non-intrusive adherence checks
  • Customizable attire checks
  • Post-deployment trainable


Request for Video

    Real Time Color Detection​

    Use cases :

    • Machine vision applications such as color sorter or food defect detection

    Highlights :

    • Color detection algorithm with real time performance
    • Detects as close to human vison as possible including color shade discrimination
    • GPGPU based algorithm on NVIDIA CUDA and Snapdragon Adreno GPU
    • Extremely low latency (a few 10s of milliseconds) for detection
    • Portable onto different hardware platforms

    Missing Artifact Detection

    Use cases :

    • Detection of missing components during various stages of manufacturing of industrial parts
    • Examples include : missing nuts and bolts, missing ridges, missing grooves on plastic and metal blocks

    Highlights :

    • Custom neural network and algorithms to achieve high accuracy and inference speed
    • Single-pass detection of many categories of missing artifacts
    • In-field trainable neural networks with dynamic addition of new artifact categories
    • Implementation using low cost cameras and not expensive machine-vision cameras
    • Learning via the use of minimal training sets
    • Options to implement the neural network on GPU or CPU based systems

    Real Time Manufacturing Line Inspection

    Use cases :

    • Detection of defects on the surface of manufactured goods (metal, plastic, glass, food, etc.)
    • Can be integrated into the overall automated QA infrastructure on an assembly line.

    Highlights :

    • Custom neural network and algorithms to achieve high accuracy and inference speed
    • Use of consumer or industrial grade cameras
    • Requires only a few hundred images during the training phase
    • Supports incremental training of the neural network with data augmentation
    • Allows implementation on low cost GPU or CPU based platforms

    Ground Based Infrastructure analytics

    Some Buildings in a city

    Use cases :

    • Rail tracks (public transport, mining, etc.)
    • Highways
    • Tunnels

    Highlights :

    • Analysis of video and images from 2D & 3D RGB camera sensors
    • Multi sensor support (X-ray, thermal, radar, etc.)
    • Detection of anomalies in peripheral areas of core infrastructure (Ex: vegetation or stones near rail tracks)

    Aerial Analytics

    Use cases :

    • Rail track defect detection
    • Tower defect detection: Structural analysis of Power
      transmission towers
    • infrastructure mapping

    Highlights :

    • Defect detection from a distance
    • Non-intrusive
    • Automatic video capture with perfectly centered ROI
    • No manual intervention is required by a pilot for
      camera positioning


    Co-founder & CEO


    Founder and Managing director of Ignitarium, Sanjay has been responsible for defining Ignitarium’s core values, which encompass the organisation’s approach towards clients, partners, and all internal stakeholders, and in establishing an innovation and value-driven organisational culture.


    Prior to founding Ignitarium in 2012, Sanjay spent the initial 22 years of his career with the VLSI and Systems Business unit at Wipro Technologies. In his formative years, Sanjay worked in diverse engineering roles in Electronic hardware design, ASIC design, and custom library development. Sanjay later handled a flagship – multi-million dollar, 600-engineer strong – Semiconductor & Embedded account owning complete Delivery and Business responsibility.


    Sanjay graduated in Electronics and Communication Engineering from College of Engineering, Trivandrum, and has a Postgraduate degree in Microelectronics from BITS Pilani.


    Request Free Demo

      RAMESH EMANI Board Member


      Board Member

      Ramesh was the Founder and CEO of Insta Health Solutions, a software products company focused on providing complete hospital and clinic management solutions for hospitals and clinics in India, the Middle East, Southeast Asia, and Africa. He raised Series A funds from Inventus Capital and then subsequently sold the company to Practo Technologies, India. Post-sale, he held the role of SVP and Head of the Insta BU for 4 years. He has now retired from full-time employment and is working as a consultant and board member.


      Prior to Insta, Ramesh had a 25-year-long career at Wipro Technologies where he was the President of the $1B Telecom and Product Engineering Solutions business heading a team of 19,000 people with a truly global operations footprint. Among his other key roles at Wipro, he was a member of Wipro's Corporate Executive Council and was Chief Technology Officer.


      Ramesh is also an Independent Board Member of eMIDs Technologies, a $100M IT services company focused on the healthcare vertical with market presence in the US and India.


      Ramesh holds an M-Tech in Computer Science from IIT-Kanpur.


      General Manager - Marketing

      A professional with a 14-year track record in technology marketing, Malavika heads marketing in Ignitarium. Responsible for all branding, positioning and promotional initiatives in the company, she has collaborated with technical and business teams to further strengthen Ignitarium's positioning as a key E R&D services player in the ecosystem.

      Prior to Ignitarium, Malavika has worked in with multiple global tech startups and IT consulting companies as a marketing consultant. Earlier, she headed marketing for the Semiconductor & Systems BU at Wipro Technologies and worked at IBM in their application software division.

      Malavika completed her MBA in Marketing from SCMHRD, Pune, and holds a B.E. degree in Telecommunications from RVCE, Bengaluru.



      VP - Operations

      Pradeep comes with an overall experience of 26 years across IT services and Academia. In his previous role at Virtusa, he played the role of Delivery Leader for the Middle East geography. He has handled complex delivery projects including the transition of large engagements, account management, and setting up new delivery centers.

      Pradeep graduated in Industrial Engineering and Management, went on to secure an MBA from CUSAT, and cleared UGN Net in Management. He also had teaching stints at his alma mater, CUSAT, and other management institutes like DCSMAT. A certified P3O (Portfolio, Program & Project Management) from the Office of Government Commerce, UK, Pradeep has been recognized for key contributions in the Management domain, at his previous organizations, Wipro & Virtusa.

      In his role as the Head of Operations at Ignitarium, Pradeep leads and manages operational functions such as Resource Management, Procurement, Facilities, IT Infrastructure, and Program Management office.


      SONA MATHEW Director – Human Resources


      AVP – Human Resources

      Sona heads Human Resource functions - Employee Engagement, HR Operations and Learning & Development – at Ignitarium. Her expertise include deep and broad experience in strategic people initiatives, performance management, talent transformation, talent acquisition, people engagement & compliance in the Information Technology & Services industry.


      Prior to Ignitarium, Sona has had held diverse HR responsibilities at Litmus7, Cognizant and Wipro.


      Sona graduated in Commerce from St. Xaviers College and did her MBA in HR from PSG College of Technology.



      Vice President - Sales

      As VP of Sales, Ashwin is responsible for Ignitarium’s go-to-market strategy, business, client relationships, and customer success in the Americas. He brings in over a couple of decades of experience, mainly in the product engineering space with customers from a wide spectrum of industries, especially in the Hi-Tech/semiconductor and telecom verticals.


      Ashwin has worked with the likes of Wipro, GlobalLogic, and Mastek, wherein unconventional and creative business models were used to bring in non-linear revenue. He has strategically diversified, de-risked, and grown his portfolios during his sales career.


      Ashwin strongly believes in the customer-first approach and works to add value and enhance the experiences of our customers.


      AZIF SALY Director – Sales


      Vice President – Sales & Business Development

      Azif is responsible for go-to-market strategy, business development and sales at Ignitarium. Azif has over 14 years of cross-functional experience in the semiconductor product & service spaces and has held senior positions in global client management, strategic account management and business development. An IIM-K alumnus, he has been associated with Wipro, Nokia and Sankalp in the past.


      Azif handled key accounts and sales process initiatives at Sankalp Semiconductors. Azif has pursued entrepreneurial interests in the past and was associated with multiple start-ups in various executive roles. His start-up was successful in raising seed funds from Nokia, India. During his tenure at Nokia, he played a key role in driving product evangelism and customer success functions for the multimedia division.


      At Wipro, he was involved in customer engagement with global customers in APAC and US.


      RAJU KUNNATH Vice President – Enterprise & Mobility


      Distinguished Engineer – Digital

      At Ignitarium, Raju's charter is to architect world class Digital solutions at the confluence of Edge, Cloud and Analytics. Raju has over 25 years of experience in the field of Telecom, Mobility and Cloud. Prior to Ignitarium, he worked at Nokia India Pvt. Ltd. and Sasken Communication Technologies in various leadership positions and was responsible for the delivery of various developer platforms and products.


      Raju graduated in Electronics Engineering from Model Engineering College, Cochin and has an Executive Post Graduate Program (EPGP) in Strategy and Finance from IIM Kozhikode.


      PRADEEP SUKUMARAN Vice President – Business Strategy & Marketing


      Vice President - Software Engineering

      Pradeep heads the Software Engineering division, with a charter to build and grow a world-beating delivery team. He is responsible for all the software functions, which includes embedded & automotive software, multimedia, and AI & Digital services

      At Ignitarium, he was previously part of the sales and marketing team with a special focus on generating a sales pipeline for Vision Intelligence products and services, working with worldwide field sales & partner ecosystems in the U.S  Europe, and APAC.

      Prior to joining Ignitarium in 2017, Pradeep was Senior Solutions Architect at Open-Silicon, an ASIC design house. At Open-Silicon, where he spent a good five years, Pradeep was responsible for Front-end, FPGA, and embedded SW business development, marketing & technical sales and also drove the IoT R&D roadmap. Pradeep started his professional career in 2000 at Sasken, where he worked for 11 years, primarily as an embedded multimedia expert, and then went on to lead the Multimedia software IP team.

      Pradeep is a graduate in Electronics & Communication from RVCE, Bangalore.


      SUJEET SREENIVASAN Vice President – Embedded


      Vice President – Automotive Technology


      Sujeet is responsible for driving innovation in Automotive software, identifying Automotive technology trends and advancements, evaluating their potential impact, and development of solutions to meet the needs of our Automotive customers.

      At Ignitarium, he was previously responsible for the growth and P&L of the Embedded Business unit focusing on Multimedia, Automotive, and Platform software.

      Prior to joining Ignitarium in 2016, Sujeet has had a career spanning more than 16 years at Wipro. During this stint, he has played diverse roles from Solution Architect to Presales Lead covering various domains. His technical expertise lies in the areas of Telecom, Embedded Systems, Wireless, Networking, SoC modeling, and Automotive. He has been honored as a Distinguished Member of the Technical Staff at Wipro and has multiple patents granted in the areas of Networking and IoT Security.

      Sujeet holds a degree in Computer Science from Government Engineering College, Thrissur.


      RAJIN RAVIMONY Distinguished Engineer


      Distinguished Engineer


      At Ignitarium, Rajin plays the role of Distinguished Engineer for complex SoCs and systems. He's an expert in ARM-based designs having architected more than a dozen SoCs and played hands-on design roles in several tens more. His core areas of specialization include security and functional safety architecture (IEC61508 and ISO26262) of automotive systems, RTL implementation of math intensive signal processing blocks as well as design of video processing and related multimedia blocks.


      Prior to Ignitarium, Rajin worked at Wipro Technologies for 14 years where he held roles of architect and consultant for several VLSI designs in the automotive and consumer domains.


      Rajin holds an MS in Micro-electronics from BITS Pilani.


      SIBY ABRAHAM Executive Vice President, Strategy


      Executive Vice President, Strategy


      As EVP, of Strategy at Ignitarium, Siby anchors multiple functions spanning investor community relations, business growth, technology initiatives as well and operational excellence.


      Siby has over 31 years of experience in the semiconductor industry. In his last role at Wipro Technologies, he headed the Semiconductor Industry Practice Group where he was responsible for business growth and engineering delivery for all of Wipro’s semiconductor customers. Prior to that, he held a vast array of crucial roles at Wipro including Chief Technologist & Vice President, CTO Office, Global Delivery Head for Product Engineering Services, Business Head of Semiconductor & Consumer Electronics, and Head of Unified Competency Framework. He was instrumental in growing Wipro’s semiconductor business to over $100 million within 5 years and turning around its Consumer Electronics business in less than 2 years. In addition, he was the Engineering Manager for Enthink Inc., a semiconductor IP-focused subsidiary of Wipro. Prior to that, Siby was the Technical Lead for several of the most prestigious system engineering projects executed by Wipro R&D.


      Siby has held a host of deeply impactful positions, which included representing Wipro in various World Economic Forum working groups on Industrial IOT and as a member of IEEE’s IOT Steering Committee.


      He completed his MTech. in Electrical Engineering (Information and Control) from IIT, Kanpur and his BTech. from NIT, Calicut


      SUJEETH JOSEPH Chief Product Officer


      Chief Technology Officer


      As CTO, Sujeeth is responsible for defining the technology roadmap, driving IP & solution development, and transitioning these technology components into practically deployable product engineering use cases.


      With a career spanning over 30+ years, Sujeeth Joseph is a semiconductor industry veteran in the SoC, System and Product architecture space. At SanDisk India, he was Director of Architecture for the USD $2B Removable Products Group. Simultaneously, he also headed the SanDisk India Patenting function, the Retail Competitive Analysis Group and drove academic research programs with premier Indian academic Institutes. Prior to SanDisk, he was Chief Architect of the Semiconductor & Systems BU (SnS) of Wipro Technologies. Over a 19-year career at Wipro, he has played hands-on and leadership roles across all phases of the ASIC and System design flow.


      He graduated in Electronics Engineering from Bombay University in 1991.


      SUJITH MATHEW IYPE Co-founder & CTO


      Co-founder & COO


      As Ignitarium's Co-founder and COO, Sujith is responsible for driving the operational efficiency and streamlining process across the organization. He is also responsible for the growth and P&L of the Semiconductor Business Unit.


      Apart from establishing a compelling story in VLSI, Sujith was responsible for Ignitarium's foray into nascent technology areas like AI, ML, Computer Vision, and IoT, nurturing them in our R&D Lab - "The Crucible".


      Prior to founding Ignitarium, Sujith played the role of a VLSI architect at Wipro Technologies for 13 years. In true hands-on mode, he has built ASICs and FPGAs for the Multimedia, Telecommunication, and Healthcare domains and has provided technical leadership for many flagship projects executed by Wipro.


      Sujith graduated from NIT - Calicut in the year 2000 in Electronics and Communications Engineering and thereafter he has successfully completed a one-year executive program in Business Management from IIM Calcutta.


      RAMESH SHANMUGHAM Co-founder & COO


      Co-founder & CRO

      As Co-founder and Chief Revenue Officer of Ignitarium, Ramesh has been responsible for global business and marketing as well as building trusted customer relationships upholding the company's core values.

      Ramesh has over 25 years of experience in the Semiconductor Industry covering all aspects of IC design. Prior to Ignitarium, Ramesh was a key member of the senior management team of the semiconductor division at Wipro Technologies. Ramesh has played key roles in Semiconductor Delivery and Pre-sales at a global level.

      Ramesh graduated in Electronics Engineering from Model Engineering College, Cochin, and has a Postgraduate degree in Microelectronics from BITS Pilani.